Blocking transition of interface traps in MoS${}_2$-on-SiO${}_2$ FETs

Electrical conductivity with gate-sweep in a few layer MoS${}_2$-on-SiO${}_2$ field-effect-transistor shows an abrupt reduction in hysteresis when cooled. The hysteresis and time dependent conductivity of the MoS${}_2$ channel are modeled using the dynamics of interface traps’ occupancy. The reduction in hysteresis is found to be steepest at a blocking temperature near 225 K. This is attributed to the interplay between thermal and barrier energies and fitted using a distribution of the latter. Further, the charge stored in the blocked traps is programmed at low temperatures by cooling under suitable gate voltage. Thus the threshold gate-voltage in nearly non-hysteretic devices at 80 K temperature is reversibly controlled over a wide range.