Placing and routing quantum LDPC codes in multilayer superconducting hardware

Quantum error-correcting codes with asymptotically lower overheads than the surface code require nonlocal connectivity. Leveraging multilayer routing and long-range coupling capabilities in superconducting qubit hardware, we develop Hardware-Aware Layout, HAL: a robust, runtime-efficient heuristic algorithm that automates and optimizes the placement and routing of arbitrary codes. Using HAL, we generate around 150 explicit layouts of quantum low-density parity-check (qLDPC) codes with topological structure – such as the bivariate bicycle codes and the open-boundary tile codes – and find that removing the periodic boundaries significantly lowers the hardware complexity with only a moderate reduction of logical efficiency. We also lay out highly nonlocal qLDPC code families – quantum radial and Tanner codes – that achieve competitive tradeoffs between hardware complexity and logical efficiency. Based on our findings, we anticipate many novel qLDPC codes to be realizable on near-term superconducting qubit hardware and inform future directions for the co-design of quantum devices and fault-tolerant architectures.