Fast polar codes for terabits-per-second throughput communications

Targeting high-throughput and low-power communications, we implement two successive cancellation (SC) decoders for polar codes. With $16nm$ ASIC technology, the area efficiency and energy efficiency are $4Tbps\mathrm{/}m{m}^2$ and $0.63pJ\mathrm{/}bit$, respectively, for the unrolled decoder, and $561Gbps\mathrm{/}m{m}^2$ and $1.21pJ\mathrm{/}bit$, respectively, for the recursive decoder. To achieve such a high throughput, a novel code construction, coined as fast polar codes, is proposed and jointly optimized with a highly-parallel SC decoding architecture. First, we reuse existing modules to fast decode more outer code blocks, and then modify code construction to facilitate faster decoding for all outer code blocks up to a degree of parallelism of $16$. Furthermore, parallel comparison circuits and bit quantization schemes are customized for hardware implementation. Collectively, they contribute to an $2.66\times$ area efficiency improvement and $33\mathrm{\%}$ energy saving over the state of the art.