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We evaluate strategies for reducing the run time of fault-tolerant quantum computations, targeting practical utility in scientific or industrial workflows. Delivering a technology with broad impact requires scaling devices, while also maintaining acceptable run times for computations. Optimizing logical clock speed may require moving beyond current strategies, and adopting methods that trade faster run time for increased qubit counts or engineering complexity. We discuss how the co-design of hardware, fault tolerance, and algorithmic subroutines can reduce run times. We illustrate a selection of these topics with resource estimates for simulating the Fermi-Hubbard model.

生成讲解博客的中文版本

生成AI智能校验的中文版本